Sign In | Join Free | My himfr.com
himfr.com

Shenzhen Olinkcom Technology Co.,Ltd

Customer demand oriented, Technological innovation, Build a first-class design and manufacturing enterprise in the optical transceiver industry.

Verified Supplier

5 Years

Home > Active Optical Cables >

3M 100G QSFP28 Passive Copper Cable Juniper Compatible

Shenzhen Olinkcom Technology Co.,Ltd
Trust Seal
Verified Supplier
Credit Check
Supplier Assessment
Contact Now
    Buy cheap 3M 100G QSFP28 Passive Copper Cable Juniper Compatible from wholesalers
     
    Buy cheap 3M 100G QSFP28 Passive Copper Cable Juniper Compatible from wholesalers
    • Buy cheap 3M 100G QSFP28 Passive Copper Cable Juniper Compatible from wholesalers

    3M 100G QSFP28 Passive Copper Cable Juniper Compatible

    Ask Lasest Price
    Brand Name : OLKOPTO
    Model Number : OLSQ8TXA-CDM1
    Certification : RoHS FCC CE GS UL FDA etc
    Payment Terms : T/T or Net 30 days
    Supply Ability : 80-120k per month
    Delivery Time : 3-5 working days
    • Product Details
    • Company Profile

    3M 100G QSFP28 Passive Copper Cable Juniper Compatible

    100G QSFP28 Passive Copper Cable 3M AOC Cables Juniper Compatible


    Juniper Networks Compatible 100G QSFP28 JNP-QSFP28-AOC-3M Active Optical Cable


    Description:

    QSFP28 Active Optical Cable (AOC) components are designed for 100GB Ethernet applications. It is designed so that 100GbE devices are designed with very high port density based on electrical and mechanical specifications. The application is 100G AOC QSFP28 Applications and 100GBASE-SR4 at 25.781Gbps per lane.


    Optical Characteristics (TOP(C) = 0 to 70 , VCC = 3.13 to 3.47 V)

    ParameterSymbolMin.TypMax.UnitNote
    Transmitter
    Operating Wavelengthλ840850860nm
    Output Optical EyeCompliant with IEEE 0802.3ae
    Receiver
    Operating Wavelength840860nm

    Electrical Characteristics (TOP(C) = 0 to 70 , VCC = 3.13 to 3.47 V)

    ParameterSymbolMin.TypMax.UnitNote
    ModSelL-Module SelectVOL00.8V
    ModSelL-Module UnselectVOH2.5VCCV
    LPMode-Low Power ModeVIL00.8V
    LPMode-Normal OperationVIH2.5VCC+0.3V
    ResetL-ResetVIL00.8V
    ResetL-Normal OperationVIH2.5VCC+0.3V
    ModPrsL-Normal OperationVOL00.4V
    IntL-InterruptVOL00.4V
    IntL-Normal OperationVOH2.4VCCV

    Active cable input electrical characteristics
    Differential Data Input VoltageVIH-VIL2001600mVpp1
    Differential Input ImpedanceRIN90100110Ω
    TX-Disable Input Voltage-LowVIL00.8V2
    TX-Disable Input Voltage-HighVIH2.0VCCV2
    TX-Fault Output Voltage-LowVOL00.8V3
    TX-Fault Output Voltage-HighVOH2.0VCCV3

    Notes:

    1. Average power figures are informative only, per IEEE 802.3ae.

    2. Measured at the BER less than 1E-12, back to back. The measure pattern is PRBS 231-1 with worst ER=4.5@ 10.3125Gb/s.

    3. Internal AC coupled

    4. TX-Disable has an internal 4.7KΩ to 10 KΩ pull-up to VccT

    5. Measure with 4.7KΩ pull-up to Vcc on host board


    Pin Description

    PinNameLogicDescription
    1GNDGround1
    2Tx2nCML-ITransmitter Inverted Data Input10
    3Tx2pCML-ITransmitter Non-Inverted Data Input10
    4GNDGround1
    5Tx4nCML-ITransmitter Inverted Data Input10
    6Tx4pCML-ITransmitter Non-Inverted Data Input10
    7GNDGround1
    8ModSelLLVTTL-IModule Select3
    9ResetLLVTTL-IModule Reset4
    10Vcc Rx+3.3V Power Supply Receiver2
    11SCLLVCMOS-I/O2-wire serial interface clock5
    12SDALVCMOS-I/O2-wire serial interface data5
    13GNDGround1
    14Rx3pCML-OReceiver Non-Inverted Data Output9
    15Rx3nCML-OReceiver Inverted Data Output9
    16GNDGround1
    17Rx1pCML-OReceiver Non-Inverted Data Output9
    18Rx1nCML-OReceiver Inverted Data Output9
    19GNDGround1
    20GNDGround1
    21Rx2nCML-OReceiver Inverted Data Output9
    22Rx2pCML-OReceiver Non-Inverted Data Output9
    23GNDGround1
    24Rx4nCML-OReceiver Inverted Data Output9
    25Rx4pCML-OReceiver Non-Inverted Data Output9
    26GNDGround1
    27ModPrsLLVTTL-OModule Present6
    28IntLLVTTL-OInterrupt7
    29Vcc Tx+3.3V Power supply transmitter2
    30Vcc1+3.3V Power supply2
    31LPModeLVTTL-ILow Power Mode8
    32GNDGround1
    33Tx3pCML-ITransmitter Non-Inverted Data Input10
    34Tx3nCML-ITransmitter Inverted Data Input10
    35GNDGround1
    36Tx1pCML-ITransmitter Non-Inverted Data
    37Tx1nCML-ITransmitter Inverted Data Input10
    38GNDGround1

    Notes:

    1. GND is the symbol for signal and supply (power) common for the module. All are common within the module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane.

    2. Vcc Rx, Vcc1 and Vcc Tx shall be applied concurrently. Vcc Rx Vcc1 and Vcc Tx may be internally connected within the module in any combination. The connector pins are each rated for a maximum current of 1000 mA. Recommended host board power supply filtering is shown below .

    3. The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple modules on a single 2-wire interface bus. When the ModSelL is "High", the module shall not respond to or acknowledge any 2-wire interface communication from the host. ModSelL signal input node shall be biased to the "High" state in the module. In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any modules are deselected. Similarly, the host shall wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

    4. The ResetL pin shall be pulled to Vcc in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by asserting "low" an IntL signal with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

    5. Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc. Vcc refers to the generic supply voltages of VccTx, VccRx, Vcc_host or Vcc1.

    Hosts shall use a pull-up resistor connected to Vcc_host on each of the 2-wire interface SCL (clock), SDA (data), and all low speed status outputs. The SCL and SDA is a hot plug interface that may support a bus topology.

    6. ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The ModPrsL is asserted "Low" when inserted and deasserted "High" when the module is physically absent from the host connector.

    7. IntL is an output pin. When IntL is "Low", it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and shall be pulled to host supply voltage on the host board. The INTL pin is deasserted "High" after completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of '0' and the flag field is read (see SFF-8636).

    8. The LPMode pin shall be pulled up to Vcc in the module. The pin is a hardware control

    used to put modules into a low power mode when high. By using the LPMode pin and a combination of the Power_override, Power_set and High_Power_Class_Enable software control bits (Address A0h, byte 93 bits 0,1,2), the host controls how much power a module can dissipate.

    9. Rx(n)(p/n) are module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines that should be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the module and not required on the Host board. For operation at 28 Gb/s the relevant standards (e.g., OIF CEI v3.1) define the signal requirements on the high-speed differential lines. For operation at lower rates, refer to the relevant standards.

    Note: Due to the possibility of insertion of legacy QSFP and QSFP+ modules into a host

    designed for higher speed operation, it is recommended that the damage threshold of the host input be at least 1600 mV peak to peak differential. Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows. In the event of the optical signal on any channel becoming equal to or less than the level required to assert LOS, then the receiver data output for that channel shall be squelched or disabled. In the squelched or disabled state output impedance levels are maintained while the differential voltage swing shall be less than 50 mVpp. In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx Squelch Disable through the 2-wire serial interface. Rx Squelch Disable is an optional function. For specific details refer to SFF-8636.

    10. Tx(n)(p/n) are module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with 100 Ohm differential terminations inside the module. The AC coupling is inside the module and not required on the Host board. For operation at 28 Gb/s the relevant standards (e.g., OIF CEI v3.1) define the signal requirements on the high-speed differential lines. For operation at lower rates, refer to the relevant standards. Due to the possibility of insertion of modules into a host designed for lower speed operation, the damage threshold of the module input shall be at least 1600 mV peak to peak differential. Output squelch, hereafter Tx Squelch, for loss of input signal, hereafter Tx LOS, is an optional function. Where implemented it shall function as follows. In the event of the differential, peak-to-peak electrical signal on any channel becomes less than 50 mVpp, then the transmitter optical output for that channel shall be squelched or disabled and the associated TxLOS flag set. Where squelched, the transmitter OMA shall be less than or equal to -26 dBm and when disabled the transmitter power shall be less than or equal to -30 dBm. For applications, e.g. Ethernet, where the transmitter off condition is defined in terms of average power, disabling the transmitter is recommended and for applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of OMA, squelching the transmitter is recommended. In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch can be deactivated using Tx Squelch Disable through the 2-wire serial interface. Tx Squelch Disable is an optional function. For specific details refer to SFF- 8636.


    Cable Mechanical Specifications

    ParameterValueUnits
    Diameter3Mm
    Minimum bend radius30Mm

    Length tolerance

    Length < 1 m: +5 /-0Cm
    1 m ≤length ≤ 4.5 m: +15 / -0Cm
    5 m ≤length ≤ 14.5 m: +30 / -0Cm
    Length≥15.0 m +2% / -0m
    Cable colorOrange(OM2),Aqua(OM3),Megenta(OM4)

    Ordering Information

    Part NumberDescription
    OLSQ8TXA-CDM1QSFP28, up to 100Gb/s, AOC, 0~70℃, with Digital Diagnostic Monitor

    Quality 3M 100G QSFP28 Passive Copper Cable Juniper Compatible for sale
    Inquiry Cart 0
    Send your message to this supplier
     
    *From:
    *To: Shenzhen Olinkcom Technology Co.,Ltd
    *Subject:
    *Message:
    Characters Remaining: (0/3000)